The present invention relates to a digital filter apparatus having a resonance characteristic.
As an alternative to an analog filter incorporating a transistor, a resistor, a capacitor, a coil or an operational amplifier, a digital filter incorporating a digital circuit such as a multiplier, an adder, or a delay circuit has recently received a lot of attention. Such a digital filter is used, for example, as a tone color setting circuit of an electronic musical instrument. These digital filters may be, for example, low-pass filters, high-pass filters and band-pass filters. For example, some analog type music synthesizers incorporate an analog filter having a resonance characteristic in order to add special tone color to the sound. When a filter having a resonance characteristic is used, a peak is generated in the amplitude of the musical sound signal and a musical sound is obtained which has a special tone color in which this frequency component is emphasized. Although it is possible to construct a digital filter having such a resonance characteristic, a ROM of large capacity as an element of the digital filter is generally necessary, resulting in a disadvantage. This will be described in more detail.
For designing a filter, a transfer function must first be obtained. A method is known for designing a digital filter according to which a transfer function H(s) of an analog filter is first obtained and then it undergoes the standard z-transform, the bilinear z-transform, or the alignment z-transform to obtain a transfer function H(z) of the desired digital filter.
An example of a second-order low-pass filter will be described. A transfer function H(s) of the second-order low-pass filter is generally expressed by ##EQU1## where H is the gain which is generally 1, Q is the amplitude of the resonance, which is 1/.sqroot.2 under the normal non-resonance condition, and .omega.O is the resonance angular frequency. Under this normal condition, the poles of this low-pass filter have two conjugate roots represented by P1, P2 of the s-plane as shown in FIG. 1 and may be expressed by the equation ##EQU2## As may be seen from the characteristic graph in FIG. 1, the poles P1, P2 move to the points (O, .+-..omega.O) on the imaginary axis (j.omega.) as Q increases according to 1/.sqroot.2, 1, 2, . . . FIG. 2 is a characteristic graph of a low-pass filter having a resonance characteristic at frequency .omega.O.
When the transfer function H(s) of equation (1) undergoes the bilinear z-transform, the transfer function H(z) of the digital filter is expressed by ##EQU3## where b1, b2, and K are constants respectively expressed by the following equations: ##EQU4## where Ts is the sampling time and z is the variable of the bilinear z-transform.
Therefore, the digital filter apparatus whose transfer function H(z) is expressed by equation (3) is constructed as shown in FIG. 3. Referring to FIG. 3, reference numeral 1 denotes an adder to which an input signal is supplied. The output of the adder 1 is supplied to another adder 2 and a sampling time (Ts) delay circuit 3. The output of the delay circuit 3 is supplied to multipliers 4 and 5. To the multiplier 4 is supplied data b1 from a ROM 6 selected by respective control data of a signal of resonance angular frequency .omega.O and Q representing the amplitude of resonance which have been supplied to the ROM 6. The input signal supplied to the multiplier 4 is multiplied by b1, and the product is supplied to the adder 1. This input signal to the adder 1 instructs the adder 1 to perform subtraction. The multiplier 5 has the function of doubling the input signal, and its output is supplied to the adder 2. The output of the delay circuit 3 is also supplied to a delay circuit 7 which delays its input signal by the sampling time (Ts). The output of the delay circuit 7 is supplied through a multiplier 8 to the adder 1 as well as directly to the adder 2. The data b2 selected by the control data supplied to the ROM 6 is supplied to the multiplier 8 for multiplication with the input signal, and the multiplication product is supplied to the adder 1. This input signal to the adder 1 instructs the adder 1 to perform subtraction. The output of the adder 2, to which are supplied the outputs of the adder 1, the multiplier 5 and the delay circuit 7 for addition thereof, is supplied to a multiplier 9. To the multiplier 9 is also supplied data K selected from the ROM 6 by the control data. The input to the multiplier 9 from the adder 2 is multiplied K times and is output.
However, with the digital filter apparatus as described above, when the amplitude of the resonance is of level n, the capacity of the ROM 6 for storing coefficients must be n times that for the case without resonance, thus demanding a ROM of very large capacity.
In general, it is the ROM which occupies a relatively large area on the semiconductor chip when integrating the digital filter. Therefore, an increase in the capacity of the ROM means a corresponding reduction in available area for elements other than the ROM on a chip of a certain area, which runs contrary to the demand for multifunctionality of the digital filter.